Группа :: Система/Ядро и оборудование
Пакет: fglrx_glx
Главная Изменения Спек Патчи Загрузить Bugs and FR
Патч: fglrx-3.7.6-sis-agp3-support.patch
--- kernel-source-fglrx-3.7.6/agpgart_be.c.sis-agp3-support 2004-04-28 19:57:09 +0400
+++ kernel-source-fglrx-3.7.6/agpgart_be.c 2004-04-28 20:07:36 +0400
@@ -3061,6 +3061,78 @@ static int __init via_kt400_setup (struc
}
+static int agp3_generic_fetch_size(void)
+{
+ u16 temp_size;
+ int i;
+ struct aper_size_info_16 *values;
+
+ pci_read_config_word(agp_bridge.dev, agp_bridge.capndx+AGPAPSIZE, &temp_size);
+ values = A_SIZE_16(agp_bridge.aperture_sizes);
+
+ for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ if (temp_size == values[i].size_value) {
+ agp_bridge.previous_size =
+ agp_bridge.current_size = (void *) (values + i);
+
+ agp_bridge.aperture_size_idx = i;
+ return values[i].size;
+ }
+ }
+ return 0;
+}
+
+static void agp3_generic_tlbflush(agp_memory *mem)
+{
+ u32 ctrl;
+ pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, &ctrl);
+ pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, ctrl & ~AGPCTRL_GTLBEN);
+ pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, ctrl);
+}
+
+static int agp3_generic_configure(void)
+{
+ u32 temp;
+ struct aper_size_info_16 *current_size;
+
+ current_size = A_SIZE_16(agp_bridge.current_size);
+
+ pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp);
+ agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+
+ /* set aperture size */
+ pci_write_config_word(agp_bridge.dev, agp_bridge.capndx+AGPAPSIZE, current_size->size_value);
+ /* set gart pointer */
+ pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPGARTLO, agp_bridge.gatt_bus_addr);
+ /* enable aperture and GTLB */
+ pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, temp | AGPCTRL_APERENB | AGPCTRL_GTLBEN);
+ return 0;
+}
+
+static void agp3_generic_cleanup(void)
+{
+ u32 ctrl;
+ pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, &ctrl);
+ pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+AGPCTRL, ctrl & ~AGPCTRL_APERENB);
+}
+
+#define AGP_GENERIC_SIZES_ENTRIES 11
+static struct aper_size_info_16 agp3_generic_sizes[AGP_GENERIC_SIZES_ENTRIES] =
+{
+ {4096, 1048576, 10,0x000},
+ {2048, 524288, 9, 0x800},
+ {1024, 262144, 8, 0xc00},
+ { 512, 131072, 7, 0xe00},
+ { 256, 65536, 6, 0xf00},
+ { 128, 32768, 5, 0xf20},
+ { 64, 16384, 4, 0xf30},
+ { 32, 8192, 3, 0xf38},
+ { 16, 4096, 2, 0xf3c},
+ { 8, 2048, 1, 0xf3e},
+ { 4, 1024, 0, 0xf3f}
+};
+
static int sis_fetch_size(void)
{
u8 temp_size;
@@ -3140,6 +3212,9 @@ static struct gatt_mask sis_generic_mask
static int __init sis_generic_setup (struct pci_dev *pdev)
{
+ u32 ncapid;
+ u8 major_version, minor_version;
+
agp_bridge.masks = sis_generic_masks;
agp_bridge.num_of_masks = 1;
agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
@@ -3166,6 +3241,23 @@ static int __init sis_generic_setup (str
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
+ switch (pdev->device) {
+ case PCI_DEVICE_ID_SI_648:
+ pci_read_config_dword(pdev, agp_bridge.capndx, &ncapid);
+ major_version = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
+ minor_version = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf;
+ if (!(major_version == 3 && minor_version >= 5))
+ break;
+ agp_bridge.aperture_sizes = agp3_generic_sizes;
+ agp_bridge.size_type = U16_APER_SIZE;
+ agp_bridge.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
+ agp_bridge.configure = agp3_generic_configure;
+ agp_bridge.fetch_size = agp3_generic_fetch_size;
+ agp_bridge.cleanup = agp3_generic_cleanup;
+ agp_bridge.tlb_flush = agp3_generic_tlbflush;
+ break;
+
+ }
return 0;
}
--- kernel-source-fglrx-3.7.6/agp.h.sis-agp3-support 2004-03-04 20:25:44 +0300
+++ kernel-source-fglrx-3.7.6/agp.h 2004-04-28 19:57:09 +0400
@@ -1129,4 +1129,43 @@ extern int __init nvidia_nforce_setup(st
#endif /* defined(__i386__) */
#endif /* LINUX_VERSION_CODE > 0x020500 */
+/* Chipset independant registers (from AGP Spec) */
+#define AGP_APBASE 0x10
+
+#define AGPSTAT 0x4
+#define AGPCMD 0x8
+#define AGPNISTAT 0xc
+#define AGPCTRL 0x10
+#define AGPAPSIZE 0x14
+#define AGPNEPG 0x16
+#define AGPGARTLO 0x18
+#define AGPGARTHI 0x1c
+#define AGPNICMD 0x20
+
+#define AGP_MAJOR_VERSION_SHIFT (20)
+#define AGP_MINOR_VERSION_SHIFT (16)
+
+#define AGPSTAT_RQ_DEPTH (0xff000000)
+#define AGPSTAT_RQ_DEPTH_SHIFT 24
+
+#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10)
+#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13)
+#define AGPSTAT_ARQSZ_SHIFT 13
+
+#define AGPSTAT_SBA (1<<9)
+#define AGPSTAT_AGP_ENABLE (1<<8)
+#define AGPSTAT_FW (1<<4)
+#define AGPSTAT_MODE_3_0 (1<<3)
+
+#define AGPSTAT2_1X (1<<0)
+#define AGPSTAT2_2X (1<<1)
+#define AGPSTAT2_4X (1<<2)
+
+#define AGPSTAT3_RSVD (1<<2)
+#define AGPSTAT3_8X (1<<1)
+#define AGPSTAT3_4X (1)
+
+#define AGPCTRL_APERENB (1<<8)
+#define AGPCTRL_GTLBEN (1<<7)
+
#endif /* _FGL_AGP_H */